1. Technical Field
The embodiments described herein are related to a semiconductor memory apparatus and, more particularly, to a circuit for generating a data input/output control signal used in a semiconductor memory apparatus.
2. Related Art
A conventional semiconductor memory apparatus includes a memory cell array having a plurality of memory cells and a peripheral circuit for storing and reading out memory cell data. The memory cell array includes a plurality of word lines and a plurality of bit lines that intersect the word lines. Each of the plurality of memory cells is positioned at an intersection of the word and bit lines. Each of the memory cells in a conventional apparatus can include a MOS transistor and a capacitor connected to the MOS transistor.
The peripheral circuit includes a row decoder for driving the word lines and a column decoder for driving the bit lines. The row decoder receives a row address and selects a specific word line, and the column decoder generates a column selection signal and selects a specific bit line, thereby selecting the specific memory cell connected the selected word and bit line. The MOS transistor of the selected memory cell is driven to store information in the capacitor, which is connected to the MOS transistor, or to read out the stored information.
Conventional semiconductor memory apparatus are driven in a high-speed operation mode. That is, since conventional semiconductor memory apparatus require high speed operations, they all operate in what is termed a high-speed operation mode regardless of the length of a column address strobe (CAS) latency.
As conventional semiconductor memory apparatus become highly integrated, the load on each bit line pair (BL and /BL) and/or on a local input/output line pair (LI0 and /LI0) is increasing. Thus, the operating margin for a conventional semiconductor memory apparatus is decreasing, and in fact hardly exists in many cases.
Conventional semiconductor memory apparatus can also operate in a low-speed operation mode; however, since almost all conventional semiconductor memory apparatus, as mentioned above, are set up for high-speed operation mode, the low-speed operation mode is also carried out under the control of the tightly restricted input/output (I/O) operation of the high-speed operation mode. As a result, a data I/O error can occur in the low-speed operation mode of a conventional semiconductor memory apparatus.